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This work presents the analog performance of strained SOI nanowires for the first time. Triple gate MOSFETs made in strained and unstrained SOI material with variable fin widths from quasi-planar transistors to nanowires with aggressively scaled fin width are compared using experimental results in the temperature range of 300K down to 10K. Intrinsic voltage gain, transconductance and output conductance...
This work aims to present the analog performance of silicon n-type and p-MOSFET SOI nanowires. Analog parameters are shown at room temperature for both n- and p-type, long and short channel devices with different channel width. Results for long channel n-MOS nanowires are investigated for the first time for low temperatures down to 100K. Moreover, an analysis is shown comparing the intrinsic voltage...
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