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The physical behavior of the dual N/P-LDMOS device concept is reviewed and analyzed. Through a proper optimization, a scalable device with good RSP vs. VBD performance in a range of 20–150 V is identified. Further, the current expansion at high gate and drain biases is fully explained by means of TCAD simulations and nicely exploited for the design of an LDO linear voltage regulator with excellent...
Degradation induced by hot-carrier stress (HCS) in a Multi-STI-Finger (MF) LDMOS is analyzed through both electrical measurements and TCAD simulations. The critical HCS issues have been first addressed on a conventional STI-based LDMOS. Then, the detrimental effect of extended Si/SiO2 interfaces along the silicon fingers in the MF-LDMOS has been widely investigated. Experimental results are analyzed...
A numerical investigation of electrical and thermal properties of a lateral trench field-plate (TFP) LDMOS is proposed. Beside the advantage in terms of specific on-resistance (RSP) vs. breakdown voltage (VBD) trade-off, achieved with a proper optimization of the geometrical and doping parameters, the use of deep trenches is discussed here with particular attention to their impact on the electrical...
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