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A high voltage LDMOS on partial silicon-on-insulator (PSOI) with a variable low-k (relative permittivity) dielectric buried layer (VLKD) and a buried p-layer (BP) is proposed (VLKD BPSOI). In the vertical direction, the low k value enhances the electric field strength in the buried dielectric (EI) and the Si window makes the substrate share the voltage drop, which leads to a high vertical breakdown...
In order to achieve a high breakdown voltage (BV) and to realize self-isolation in high-voltage ICs (HVICs), a novel high-voltage n-channel lateral double-diffused MOS (LDMOS) with a buried n-island layer (BNIL) placed at the interface between a p-type silicon-on-insulator (SOI) layer and a buried-oxide (BOX) layer (BNIL SOI) is proposed. Its breakdown mechanism is investigated theoretically and experimentally...
In this paper, a double RESURF LDMOS with optimized ESD robustness is proposed. By implanting P+ at the drain region, an additional discharge path through a vertical PNP is formed. The current density at the source side is reduced, thus it restrains the triggering of the parasitic lateral NPN. The discharge limits under ESD stress of this structure is altered from the triggering of the parasitic lateral...
The partial SOI structure of VDMOS is proposed in paper. The transient radiation and single-event-effect characteristics of the device are discussed. The results are shown that the transient radiation toleration of the partial SOI VDMOS is twice times than that of the conventional VDMOS with the same excellent power characteristics, single-event-effect toleration of the partial SOI VDMOS is more than...
In this paper, a novel substrate engineered power MOSFET with partial floating buried-layer is proposed. The proposed LDMOS with 2 mum thin epitaxial layer is designed . It is demonstrated that new electric field generated by the buried-layer modulates electric field in drift region and the voltage handling capability is enhanced. Influences of length, thickness and doping concentration of the buried-layer...
In this paper, a new analytical model for the surface electrical field distributions of double RESURF LDMOS is presented. Based on the 2-D Poisson solution, the model gives the influence on the surface electrical field in terms of the drain bias and structure parameters, such as the doping concentration, the depth and the position of the P-top region, the thickness and the doping concentration of...
In this paper, a new analytical model for the surface electrical field distributions of double RESURF LDMOS is presented. Based on the 2-D Poisson solution, the model gives the influence on the surface electrical field in terms of the drain bias and structure parameters, such as the doping concentration, the depth and the position of the P-top region, the thickness and the doping concentration of...
A novel concept of REBULF (REduced BULk Field) is proposed for the development of smart power integrated circuit with thin epitaxy layer, and a new device structure of Reduced BULk Field LDMOS with N+-floating layer embedded in the high-resistance substrate is designed. The mechanism of improved breakdown characteristics is that the high electric field around the drain is reduced by N+-floating layer...
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