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We compare As and P extension implants for NMOS Si bulk FinFETs with 5nm wide fins. P implanted FinFETs shows improved ION, +15% with Room Temperature (RT) ion implantation (I/I) and +9% with hot I/I, keeping matched Short Channel Effects (SCE) for gate length (LG) of 30nm compared with As implanted FinFETs. Based on TCAD work, P increases activated dopant concentration in extension compared with...
The influence of thinning standard 130-nm CMOS technology device wafers to residual silicon thicknesses of 20 and 5 mum has been studied. Electrical performance was evaluated at wafer level by characterizing various basic device parameters before and after thinning. An increase in the well sheet resistance and a reduction in the gate leakage current were observed. However, both at 25degC and 100degC,...
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