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This paper proposes a novel approach for the generation of test patterns suitable for detecting Gate Delay Faults (GDFs). The key idea lies in associating any single Gate Delay Fault to a set of Transition Delay (TD) Faults, and exploiting this relationship to produce effective patterns. The approach encompasses several steps: once a Gate Delay Fault is translated into a set of equivalent Transition...
With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. Several works analyze the impact of intra-cell defects w.r.t. the test quality. However, to the best of our knowledge, none of them target intra-cell defects affecting scan flip-flops. This paper presents an evaluation of the effectiveness of the ATPG test patterns in terms of intra-cell...
This work presents a single-supply SPARC 32b V8 microprocessor designed with Ultra Low Voltage (ULV) adapted standard cells and memories, aiming at low energy operation and stand by power. The microprocessor, equipped with 10 Transistors ULV bitcell 8KB SRAM cache, has been fabricated in Fully Depleted Silicon On Insulator (FDSOI) 28nm technology. A comparative analysis with similar implementations...
Biological membranes play a central role in the biology of the cell. They are not only the hydrophobic barrier allowing separation between two water soluble compartments but also a supra-molecular entity that has vital structural functions. Notably, they are involved in many exchange processes between the outside and inside cellular spaces. Accounting for the complexity of cell membranes, reliable...
In this paper, we investigate the generation of diagnostic test vectors targeting the intra-cell defects. Experimental results carried out on an industrial circuit show that we actually increase the diagnosis resolution by adding few more diagnostic test patterns.
VIsinin-LIke Proteins (VILIPs) are a subfamily of the Neuronal Calcium Sensor (NCS) proteins, which possess both N-myristoylation and EF-hand motifs allowing for a putative ‘calcium–myristoyl switch’ regulation mechanism. It has previously been established that myristoyl conjugation increases the affinity of proteins for membranes, but, in many cases, a second feature such as a cluster of positively-charged...
Novel scanning probe microscopy method of near field imaging of laser radiation is proposed. The method providing a submicron spatial resolution is based on detection of a shift of the probe resonance related to its heating by absorbed radiation. The method has been realized with a conventional silicon probe and has been employed for visualization of infrared emission from a half-disk semiconductor...
This paper presents an evaluation framework for functional programs. Programs are evaluated w.r.t. functional and structural metrics. The goal is to verify if the targeted functional programs can be re-used for verification and test purposes.
In this paper we propose a novel Power Supply Noise (PSN) sensor. It is based on timing uncertainty measure. Compared to state of the art it allows to measure the PSN events in more accurate way. The proposed sensor is actually under validation and patent reviewing process.
3D-IC test becomes a challenge with the increasing number of TSVs and demands for effective 3D aware test techniques. In this work, we propose a timing aware model to capture delay variations on a path due to resistive open TSVs. The key idea is to analytically model delay and apply our correlation-based resistive open TSV detection method to attain path delay fault coverage. We propose two methods...
Through-Silicon-Vias (TSVs) are the key enablers of 3D integration technology. Therefore, the reliability of 3D-ICs rely on the quality of TSV testing. TSVs are prone to defects that may introduce small delay variations that can cause quality and reliability issues. Moreover, physical and electrical conditions, such as TSV dimensions, coupling and IR-drop, may affect path delay variations and consequently...
With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.
Power-gating techniques have been adopted so far to reduce the static power consumption of an Integrated Circuit (IC). Power gating is usually implemented by means of several power switches. Manufacturing defects affecting power switches can lead to increase the actual static power consumption and, in the worst case they can completely isolate a functional block of the IC. In this paper we present...
Physical Design (PD) issues are becoming a major challenge with technology scaling in integrated circuits. Multi-aggressor crosstalk, power supply noise and ground bounce are some of the PD issues that cause considerable path delay variations. Therefore, these PD issues need to be considered during path delay testing to ensure better delay defect coverage. In this paper, we first show that the path...
CMOS technology trends at one side open up some opportunities like making small and power efficient devices available, which in turn allow to put more functionality into a single chip. However, on the other side it poses some challenges like making devices vulnerable to hard and soft errors. In this paper we propose an efficient fault-tolerant architecture able to deal with permanent and transient...
Si le risque de néoplasie est clairement augmenté dans les autres myosites inflammatoires comme la dermatomyosite et la polymyosite, il n’existe pas de preuve dans la littérature d’une association entre syndrome des antisynthétases et néoplasie.Nous rapportons l’observation d’un patient de 54ans, tabagique, avec syndrome des antisynthétases, anticorps anti-Jo1 positifs, ayant fait découvrir un adénocarcinome...
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