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High speed dynamic logic implementations have power consumption bottlenecks when driving large capacitive loads that occur in clock trees, memory bit/word lines and I/O pads. This severely limits their use in a System on Chip (SoC) at Gigabit rates. A novel dynamic logic gate that saves switching power by 50% with LC resonance is described. The stored energy on the load capacitance is transferred...
High speed dynamic logic implementations have power consumption bottlenecks when driving large capacitive loads that occur in clock trees, memory bit/word lines and I/O pads. This severely limits their use in a System on Chip (SoC) at Gigabit rates. A novel dynamic logic gate that saves switching power by 50% with LC resonance is described. The stored energy on the load capacitance is transferred...
Global Systems for Mobile communications (GSM) traditionally use linear drop out regulators (LDO) to power the different components of the system. LDOs have excellent noise performance and low power efficiency while switching regulators offer higher efficiency but have large spurs occurring at integer multiples of the clock frequency. In this work, a switching regulator that has a delta sigma (ΔΣ)...
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