The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A method for designing $LC$ tank circuits to improve energy efficiency and reduce layout area is described. The approach uses a projected shield that is floating, overlaps the trace of the overlying inductor, and adds capacitance to the tank’s inductor. Capacitance is distributed along the spiral traces, and the layout area is thus decreased. In this paper, we investigate the properties of spiral...
An energy efficient and area saving local clocking scheme using new resonant techniques is illustrated with a bank of 1024 flip-flops. Energy recovering pulsed resonant (PR) clocking is designed to drive explicit-pulsed negative setup time latches. A pre-driver that generates tracking pulses at each transition of clock for dual edge (DET) operation is robust across PVT. While both the pre-driver and...
High speed dynamic logic implementations have power consumption bottlenecks when driving large capacitive loads that occur in clock trees, memory bit/word lines and I/O pads. This severely limits their use in a System on Chip (SoC) at Gigabit rates. A novel dynamic logic gate that saves switching power by 50% with LC resonance is described. The stored energy on the load capacitance is transferred...
High speed dynamic logic implementations have power consumption bottlenecks when driving large capacitive loads that occur in clock trees, memory bit/word lines and I/O pads. This severely limits their use in a System on Chip (SoC) at Gigabit rates. A novel dynamic logic gate that saves switching power by 50% with LC resonance is described. The stored energy on the load capacitance is transferred...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.