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A scalable 7.0-Gb/s/lane, 6-lane serial link transceiver for chip-to-chip NRZ data communication is described. Its serializing transmitter uses a new circuit topology, with data-controlled pulse generation followed by pulse-controlled serialization, and provides improved bandwidth and power efficiency with the elimination of on-chip NRZ signaling and retiming while preserving the bandwidth benefit...
On-chip low skew clock distribution driving large load capacitances can consume as much as 70% of the total dynamic power that is lost as heat, resulting in high cooling costs. To mitigate this, an energy recovering reconfigurable series resonance solution with all the critical support circuitry is described. This resonant clock driver on a 22 nm process node saves about 50% driver power (40%...
An energy efficient and area saving local clocking scheme using new resonant techniques is illustrated with a bank of 1024 flip-flops. Energy recovering pulsed resonant (PR) clocking is designed to drive explicit-pulsed negative setup time latches. A pre-driver that generates tracking pulses at each transition of clock for dual edge (DET) operation is robust across PVT. While both the pre-driver and...
High speed dynamic logic implementations have power consumption bottlenecks when driving large capacitive loads that occur in clock trees, memory bit/word lines and I/O pads. This severely limits their use in a System on Chip (SoC) at Gigabit rates. A novel dynamic logic gate that saves switching power by 50% with LC resonance is described. The stored energy on the load capacitance is transferred...
High speed dynamic logic implementations have power consumption bottlenecks when driving large capacitive loads that occur in clock trees, memory bit/word lines and I/O pads. This severely limits their use in a System on Chip (SoC) at Gigabit rates. A novel dynamic logic gate that saves switching power by 50% with LC resonance is described. The stored energy on the load capacitance is transferred...
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