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This paper describes a fractional-N subsampling PLL in 28nm CMOS. Fractional lock is achieved by using a 10bit digital-to-time converter (DTC) that generates a delayed sampling clock with minimal impact on PLL performance. Background calibration guarantees appropriate DTC gain, reducing spurs. The system achieves −38 dBc of integrated phase noise (280fs RMS jitter) at 10GHz when a worst-case fractional...
This paper presents an efficient mitigation approach for duty cycle mismatch of in-phase and quadrature upconversion signals in digital transmitters. This approach is supported by a mathematical analysis of the baseband equivalent impact of duty cycle mismatch. An efficient digital pre-distortion method is proposed to eliminate the distortion impact. Simulation results show that, for both 64-QAM and...
As a disruptive solution exploiting the intrinsic speed of deeply scaled CMOS technology, digital RF transmitter has attracted extensive attention for its capability to handle multiple radio standards. However, deeply scaled nano level technology has both pros and cons, so that state-of-the-art designs still suffer from the combination of a large number of non-idealities that are inherent in deeply...
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