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Lowering the supply voltage of StaticRandom-Access Memories (SRAM) is key to reduce anintegrated circuit power consumption, however since thisbadly affects the circuit performances, it might lead tovarious failure modes of the memory circuit. While itis known that assist techniques can help in recoveringfunctionality, it is hard to find a detailed model of thosetechniques. In this work, static write-...
The silicon thickness (Tsi) fluctuation monitoring on FD-SOI 28nm technology process is addressed by 2 different electrical characterization techniques. The first, capacitive, is adapted to within wafer variations and lot/wafer variations monitoring. The second, using the Idsat sensitivity to the Tsi in an addressable transistors array, allows to measure the local variations in the range of few tens...
We designed an addressable transistors array to analyse local variability at the wafer scale. On FDSOI substrates, we measure no impact of the silicon thickness variations on short channel transistors, and demonstrate that the impact on large area transistors is no more visible when the Tsi is well controlled.
Following the circuit integration trend, the process monitoring structures need to predict the production circuits reliability while keeping test time small and preserving the wafer area. The design presented monitors a 40nm CMOS bitcell failure evolution with supply voltage within a 260kb SRAM matrix and reports the number of fails through an integer-to-current converter. It approximates huge population...
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