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The development of energy efficient hardware has been a trend in microprocessor design for the last two decades. VLIW processors are a representative example, since they have a simpler design and competitive performance, because their ILP exploitation is done statically by the compiler. In this paper, we study the energy savings that could be obtained by adapting such microarchitecture according to...
The susceptibility of SRAM-based FPGAs to soft errors increases with each technology node due to the reduction of transistor size, the reduction of voltage supply and the increase of density of devices. This work presents the actual impact of voltage reductions for neutron-induced soft errors in SRAM-based FPGAs. We run neutron radiation experiments with a Spartan-6 (45nm) FPGA at different supply...
This paper presents the Matrix Operation Microprocessor Architecture (MoMa) for reliable embedded computing. MoMa introduces a software execution mechanism based on transactions, which provides a localized error correction scheme that leads to reduced error correction latency and hardware redundancy without incurring on expensive execution check pointing. Coupled to the transactional software execution...
The ever-increasing complexity of applications covered by wireless sensor networks (WSNs) demands for increasing memory size, which in turn increases the power drain. It is well known that SRAM power consumption can be reduced by employing a banked structure, where unused banks are switched into the low leakage retention mode. In this work, we propose a new strategy for memory banking, taking advantage...
This paper presents an approach to detect SEEs in SRAM-based FPGAs by using software-based techniques combined with a nonintrusive hardware module. We implemented a MIPS-based soft-core processor in a Virtex5 FPGA and hardened it with software- and hardware-based fault tolerance techniques. First fault injection in the configuration memory bitstream was performed in order to verify the feasibility...
A novel fault-tolerant microprocessor capable of detecting and correcting radiation-induced soft errors is proposed and evaluated. The Resilient Adaptive Algebraic Architecture performs time redundancy in parallel with matrix multiplication computation, guaranteeing on-the-fly detection and correction of errors disrupting data and logic with minimum overhead. We evaluate the RA3 microprocessor in...
A novel fault-tolerant microprocessor capable of detecting and correcting radiation-induced soft errors is proposed and evaluated. The Fault-Tolerant Algebraic Architecture (FTAA) performs time redundancy intrinsically with computation, guaranteeing on-the-fly detection and correction of errors disrupting data and logic with minimum overhead. We evaluate the FTAA microprocessor in terms of performance,...
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