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This paper presents the principle and design of an SOI-CMOS low noise chopper amplifier for electronic data acquisition system in down-hole-drilling application that operates at the high temperature (>170 ºC) regime. The chopper amplifier is designed to have three-stages where the first stage is a folded cascade. A commercially available 1-μm SOI-CMOS technology was chosen. Simulations showed that...
The digital compensation method for path delay mismatches in time-to-digital converter (TDC) based on gatedring oscillator (GRO) is proposed and demonstrated. The output of the GRO is digitized by the combination of a counter and a phase-to-digital converter producing an integer and a fractional digital value, respectively. Due to the delay mismatches between two paths, the integer and fractional...
A low noise, 250-MHz fifth order 0.1 dB ripple chebyshev Gm-C filter, with a discrete tuning scheme in 0.18-μm CMOS is presented. The tuning circuit employs an amplitude locked loop (ALL) to find the correct tuning word to maintain fc within 250MHz ±5% for VDD variation of 1.8±0.1V, temperature variation of −40°C to 125°C and across process corners. Compared to conventional tuning schemes, proposed...
In this letter, a high-gain and selectivity W-band LNA using 0.13 SiGe BiCMOS is proposed. A Q-enhanced cascode approach with a filter synthesis passband-forming technique was employed to achieve gain and selectivity improvement simultaneously. The amplifier achieved a gain of above 45 dB and a noise figure of 6–8.3 dB at 77–101 GHz with a power consumption of 19.2 mW. The LNA has high...
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