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A performance-evaluation simulator, such as a cycle-accurate simulator, is a key tool for exploring appropriate asynchronous Network-on-Chip (NoC) architectures in early stages of VLSI design, but its accuracy is insufficient in practical VLSI implementation. In this paper, a highly accurate performance-evaluation simulator based on a delay-aware model is proposed for implementing an appropriate asynchronous...
This paper presents a high-performance asynchronous data-transfer circuit based on a multiple-valued current-mode single-track scheme for on-chip communication. Since one-bit data and control information are represented by using a multi-level signal in the proposed single-track scheme, one-bit data can be transmitted asynchronously using a single wire between modules. The use of current-mode signaling...
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