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A low power consumption and wide locking-range divide-by-six injection-locked frequency divider is demonstrated. Instead of directly using the high-order harmonics generated by nonlinearity, the proposed structure employs the down-conversion mixing two times to provides a strong injection-locking signals. The measured locking-range is from 15.6GHz to 21.8GHz (33%) with an injection power of 0dBm....
A PMOS switching-biased VCO is investigated and fabricated by using TSMC 0.35 μm CMOS technology with 2.8 V power supply voltage. A switching bias is employed for the PMOS tail transistor to improve the phase noise. Measured tuning range is ranged from 2.87 GHz to 3.2 GHz. At 1 MHz offset from the carrier, the measured phase noise is −118.2 dBc/Hz. The chip takes 0.32 mm2 area. For a 0.35mm process,...
A wideband bandpass filter topology is proposed with three plane capacitors attached to the symmetrical coupled three-line microstrip structure. It shows a quasi-elliptic wideband response with two transmission zeros added so as to enhance the selectivity. This structure demonstrates 51% bandwidth with good insertion/return losses, flat group delay, sharp transition, and embedded DC-chock.
A divide-by-3 direct-injection-locked frequency divider is demonstrated with an extra divide-by-2 operation by utilizing the two-fold frequency at the common-node between the drain-pumped injectors. The effective transconductance of the injectors is increased due to the existence of divide-by-two locking circuitry. The measured locking range is from 11.77 to 16.64 GHz (34.28%) with an output power...
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