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Wire width optimization for SADP process is addressed, which involves a decision of how cut- and block-masks should form; a goal is to reduce wire delay in timing critical paths. The problem is formulated using a graph: a vertex corresponds to wire segment with its maximum length for widening as a vertex weight; an edge represents a potential conflict between two candidate wire segments that we wish...
Line-end cut process has been used to create very fine metal wires in sub-14nm technology. Cut patterns split regular line patterns into a number of wire segments with some segments being used as actual routing wires. In sub-7nm technology, cuts are smaller than optical resolution limit, and a directed self-assembly lithography with multiple patterning (MP-DSAL) is considered as a patterning solution...
Airgap refers to a void inserted in some inter metal dielectric (IMD). It brings about reduced permittivity and corresponding reduction in coupling capacitance. We address a problem of selective airgap insertion in clock wires to reduce clock skew as well as power consumption. This is performed after conventional clock tree construction and optimization, so the reduction in clock skew due to inserted...
Crosslinks may be inserted in a few clock tree nodes to reduce on-chip variation induced clock skew, simply called OCV skew. A change in clock transition and clock latency should be accurately estimated and be reflected in crosslink insertion algorithm, which we study. Fast estimation of OCV skew is important, which we also address. Crosslink insertion problem is modeled into a graph, and is solved...
A clock mesh, in which clock signals are shorted at mesh grid, is less susceptible to on-chip process variation, and so it has widely been studied recently for a clock network of smaller skew. A practical design may require more than one mesh primarily because of hierarchical clock gating architecture; a single mesh, however, can also support the same architecture after some hierarchies are removed...
Data retention is important to avoid data loss in power-gated circuits. Isolation circuitry should be used to keep output value as well as to avoid floating; a flip-flop capable of data retention, called retention flip-flop, should be used to keep flip-flop state. Examples of their implementations are reviewed. Due to extra circuitry and wires they introduce, it is important to understand how much...
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