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The Wave Dynamic Differential Logic (WDDL) offers an effective way to resist Side Channel Attacks (SCA). But, it suffers from early propagation and routing imbalance between dual signals. In this paper, we deal first with the EPE problem. We study the security of BCDL logic, which is known to counter early propagation, and we compare it to WDDL logic. We target a custom tree-based FPGA of 2048 cells...
The Tree-based FPGA offers better density and timing determinism than traditional mesh-based FPGA. Moreover, thanks to its multilevel structure, it offers greater easiness to balance dual signals in terms of routing resources number. In this paper, we study the use of the Wave Dynamic Differential Logic (WDDL) on a custom tree-based FPGA of 2048 cells. The WDDL technique offers an effective way to...
Probing attacks are serious threats on integrated circuits. Security products often include a protective layer called shield that acts like a digital fence. In this article, we demonstrate a new shield structure that is cryptographically secure. This shield is based on the newly proposed SIMON lightweight block cipher and independent mesh lines to ensure the security against probing attacks of the...
This paper presents the design methodology of a metastability-based True Random Number Generator (TRNG) on a Xilinx FPGA. As its structure is based on an open-loop delay chain, it provides both high throughput and security against physical attacks since it is not sensitive to coupling attacks as for oscillator-based TRNG. The proposed architecture, implemented in a Virtex-5 XC5VLX50T, uses 4% of the...
This paper presents an easy to design Physically Unclonable Function (PUF). The proposed PUF implementation is a loop composed of identical and controllable delay chains which are serially assembled in a loop to create a single ring oscillator. The frequency discrepancies resulting from the oscillator driven by complementary combinations of the delay chains allows to characterize one device. The...
Recently, some active shielding techniques have been broken (e.g. by FlyLogic). The caveat is that their geometry is easy to guess, and thus they can be bypassed with an affordable price. This paper has two contributions. First of all, it provides a definition of the objectives of shielding, which is seldom found in publicly available sources. Notably, we precise the expected functionality, but also...
Dual-rail precharge logic (DPL) are hardware countermeasures deployed to protect cryptographic coprocessors. However, their implementation on FPGA has been an issue of concern mainly due to imbalanced routing and early propagation effect. We analyzed the causes due to which DPL implementation on FPGA usually fails and previously proposed solutions. Many articles report that early propagation effect...
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