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A methodology is described to determine the distribution of current within a power network for use in CMOS standard cell integrated circuits based on exploratory information about the power network. Models are presented to extrapolate the noise within power networks in 14, 10, and 7 nm CMOS technologies. Stripes, interconnect between local power rails, are evaluated as a means to reduce power noise,...
Since the minimum feature size has shrunk beyond the sub-30-nm node, power density has become the major factor in modern microprocessors. Techniques such as dynamic voltage scaling operating down to near threshold voltage levels and supporting multiple voltage domains have become necessary to reduce dynamic as well as static power. A key component of these techniques is a level shifter that serves...
Near threshold circuits (NTC) are an attractive and promising technology that provides significant power savings with some delay penalty. The feasibility of NTC technology with MOS Current Mode Logic (MCML) based on a 14 nm FinFET process node is examined in this paper. A 32 bit Kogge Stone adder is chosen as a demonstration vehicle for simulation and feasibility analysis. MCML yields enhanced power...
Memristive devices are novel structures, developed primarily as memory. Another interesting application for memristive devices is logic circuits. In this paper, MRL (Memristor Ratioed Logic) — a hybrid CMOS-memristive logic family — is described. In this logic family, OR and AND logic gates are based on memristive devices, and CMOS inverters are added to provide a complete logic structure and signal...
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