The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The NMOSFET-only pass gates used in some digital CMOS applications, such as the Field-Programmable Gate Arrays (FPGAs), are apparently vulnerable to Positive Bias Temperature Instability (PBTI). Here we discuss the impact of PBTI frequency and workload on high-k/metal-gate NMOSFETs in terms of Capture-and-Emission Time (CET) maps and quantitatively explain the degradation of our test circuit. From...
Liner coverage in the via plays a critical role on via depletion EM for dual damascene Cu interconnects. Poor liner coverage at the via bottom often results in early EM fails. On the other hand, if the liner at via bottom is permeable to Cu diffusion, thanks to the constant Cu supply into the via from the line below, a very long or even “immortal” EM failure mode can be observed. This paper discusses...
Selective CVD Ru cap deposition process has been developed for BEOL Cu/low-k integration. Selectivity of CVD Ru deposition between Cu and dielectrics is investigated. Electrical performance, electromigration (EM) lifetime, voltage ramp (I-V), and time-dependent-dielectric-breakdown (TDDB) are also characterized for Cu interconnects capped with CVD Ru. This selective CVD Ru cap process is a good candidate...
The study of low-k TDDB line space scaling is important for assuring robust reliability for new technologies. Although spacing effects due to line edge roughness (LER) on low-k TDDB lifetime were reported previously (Chen et al., 2007; Lloyd et al., 2007; Kim et al., 2007), there has been a lack of an analytical model with which to link line edge roughness to experimental TDDB data in a simple quantitative...
Thin film characterization, electrical performance, and preliminary reliability of physical vapor-deposited (PVD) TaN/chemical vapor-deposited (CVD) Ru bilayer were carried out to evaluate its feasibility as a liner layer for back-end of line (BEOL) Cu-low k integration. Adhesion and barrier strength were studied using 4-point bend, X-ray diffraction (XRD), and triangular voltage sweep (TVS) techniques...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.