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The influence of via density and passivation thickness on the mechanical integrity of Back-End-Of-Line (BEOL) interconnects under Chip Package Interaction (CPI) loading is evaluated using a dedicated package test chip with 4 metal layers, and advanced copper/low-k processing. The reliability assessment is done using thermal cycling reliability tests, where two dedicated resistance based CPI test structures...
In this paper we present the concept of the Fully Self Aligned Via (FSAV) with motivation of achieving manufacturable litho process windows for patterning vias in 5nm-node interconnects. A process flow is proposed for FSAV which includes metal recess etching and insertion of an etch stop layer. Integration challenges for this flow are addressed and solutions demonstrated with complementary capacitance...
The influence of via density on the mechanical integrity of Back-End-Of-Line (BEOL) interconnects under Chip Package Interaction (CPI) loading is evaluated using a dedicated package test chip with 4 metal layers, and different via densities interconnecting the first 3 metal layers where the bottom two metal layers employ advanced low-k materials with k = 2.4 and have a low-k/metal ratio density of...
We report for the first time a highly selective CVD Co deposition on Cu to fill a 45nm diameter 3:1 aspect ratio via in a Cu dual damascene structure. We have achieved void-free Co fill of the via, demonstrating that a selective bottom-up via fill with Co is a potentially viable approach. Defect formation and control in the process and device integration are discussed. This selective process provides...
Among the technological developments pushed by the emergence of 3D Stacked IC technologies, temporary wafer bonding has become a key element in device processing over the past years. Today, although solutions for wafer support systems have made great progress in terms of process performance, thin wafer debonding and handling remains extremely challenging. Our motivation to move away from thermoplastic...
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