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Based on the bias control technique for RF power amplifiers, this paper discusses the design of automatic temperature compensation software which can accurately control the gate voltage of RF power amplifiers with the variation of the temperature. At first the paper analyzes the temperature characteristics of RF power amplifiers, and then a solution to automatically implement temperature compensation...
An intelligent gate voltage control system is proposed in accordance with changes of temperature and drain current. The system is implemented in an embedded ARM platform ADuC7026 (ARM7), in which the uC/OS-II operating system is utilized to the control the compensation process for the deterioration of the LDMOS power amplifier (PA) at different temperatures in real-time. With the interrelation of...
There has been a growing interest in robotic relay networks for applications in dangerous and hazardous environments. In particular, a team of robots with onboard radios deployed in an unknown environment would coordinate to form an ad-hoc relay network that maximizes the connectivity to transmit data from a set of unknown data sources to a gateway. In this paper, we present a problem and solutions...
A novel switch-mode power amplifier based on a Cascaded multicell multilevel circuit topology is introduced in the paper. The article lays emphasis on the design of the sliding mode controller of a multilevel class-D power amplifier and deduces the sliding mode controller's parameters. The multilevel class-D power amplifier's multi-channel PWM gate circuit based on Field Programmable Gate Array (FPGA)...
This paper presents a full custom design of an energy-efficient and high-performance add-compare-select (ACS) unit. The ACS circuit is a main building block in a state-parallel architecture based Viterbi decoder implementation. The proposed ACS circuit is implemented in 90 nm CMOS using static logic. A standard ACS circuit is also implemented for comparison purposes. The proposed ACS circuit provides...
The intrinsic FinFET device structure can provide an estimated 10-20% reduction in delay relative to planar FETs at the 22 nm technology node due to superior electrostatics. However, FinFETs are more prone to parasitic resistance and capacitance due to the thin body channel and 3-dimensional device architecture. Here we present strategies for minimizing FinFET parasitic resistance, and discuss overall...
In wireless ad hoc networks, in order to prolong network life time and improve network capacity, it is necessary to reduce large transmission power of nodes. Due to the random distribution of nodes, traditional topology control algorithms fail to solve this problem completely. So we propose a distributed movement control algorithm to solve this problem. Target locations and redundant nodes are identified...
The Toffoli gate is an especially important case of the quantum gates. In this paper, we show how to construct Toffoli gates using several additional (ancilla) photons, linear optical instruments and cross-Kerr nonlinearities. Then they are expanded to implement Extended Toffoli gates (ETOF). Our work shows only one n-IPC (n-input parity check) gate plus at most 2m CNOT or NCNOT gates can implement...
While online shopping are becoming more accepted by people in modern life, cardholders are more concerned about card fraud and the lack of cardholder authentication in the current online credit card payment. This paper proposes a purchase protocol with live cardholder authentication for online transaction which combines telephone banking and online banking together. The order information and payment...
This paper formulates and studies a model of neural network under a time-varying environment. Without assuming the smoothness, monotonicity and boundedness of the activation functions, the existence and global exponential stability of an unique equilibrium are investigated. Ourap-proach is based on the Brouwer's fixed point theorem, Banach fixed point theorem, and Halanay-type inequality.
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