The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
For the first time, we have successfully fabricated the Vth controllable connected multigate FinFET on the world's thinnest 9-nm-thick extremely thin (ET) BOX SOI substrate. It was experimentally demonstrated that, by controlling the back (substrate) bias, the Vth of the FinFET on the ETBOX is flexibly tuned from low Vth to high Vth with keeping low sub-threshold slope.
As the scaling of conventional MOSFETs approaches its technological limit, the double-gate (DG) MOSFETs have emerged as an important candidate for the next generation device. As a novel device with an additional fourth terminal, the DG devices have a potential to evolve not only in the More-Moore way, i.e. short channel effects and variation prevention, but also in the More-than-Moore direction, i...
The area penalty, operation stability, and operation speed of the 20-nm-ZG FinFET SRAM were compared to those of the 20-nm-ZG bulk-planar SRAM. The FinFET SRAM with beta-ratio of 1 is expected to realize not only 7% less area penalty, but also the same or superior operational stability to that of the bulk-planar SRAM with beta-ratio of 2 because of less variability of the device performance. Also,...
We have developed a new interlayer technology that attains a 50% reduction in capacitance and keeps good process compatibility with current Chemical Mechanical Polishing (CMP) based multi-level metallization (MLM) processes. This technology uses fluorinated amorphous carbon (a-C:F) with a dielectric constant of 2.3, sandwiched between layers of SiO/sub 2/, which are formed sequentially by high density...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.