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A 14-b 100-MS/s pipeline analog-to-digital converter (ADC) is presented. The ADC uses six 4-b stages with 2-b interstage redundancy to relax the requirements of Sub-ADC nonlinearity and interstage offset. The ADC, implemented in a 0.18-μm CMOS process, achieves 70.3-dB signal-to-noise and distortion ratio (SNDR), 83.7-dB spurious free dynamic range (SFDR) and 11.3 effective number of bit (ENOB) with...
This paper presents a 3rd order single loop continuous-time sigma-delta modulator (CTSDM) based on a 4-bit 2b/cycle SAR quantizer which reduces power consumption and chip area. The proposed high speed 2b/cycle SAR quantizer employs switchback capacitor switching procedure to obtain a more power efficient quantizer and a smaller variation of common-mode voltage which alleviates the effect of dynamic...
A 0.5V 6-to-10b rate-resolution scalable SAR ADC with microwatt power consumption is presented. Employing the successive approximation register (SAR) architecture, the proposed ADC exhibits the sampling rates of 125kS/s, 150kS/s and 250kS/s at scalable resolutions of 10b, 8b and 6b, respectively. A low-leakage voltage boosting technique is proposed, which reduces the leakage of MOS switches by 99%...
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