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Models for cache yield and coverage for radiation-induced soft errors quantify the trade-off between the minimum supply voltage (VMIN) and the soft-error protection when applying error-correcting codes (ECC) to a cache. Model predictions of the VMIN benefit and soft-error coverage agree closely with silicon measurements from a 7Mb data cache in a 20nm test chip when considering either single-error...
Supply voltage (VCC) scaling is the most effective technique for reducing the energy consumption of microprocessors. Since VCC scaling increases the impact of parameter variations on circuit performance and functionality, circuits eventually fall out of specification, thus limiting the minimum operating supply voltage (VCCMIN) for the microprocessor. The last-level cache (LLC) often determines VCCMIN...
Built-in resiliency features enable a microprocessor to detect and correct errors due to fast dynamic voltage droop events as well as other types of dynamic variations. Timing errors in the microprocessor core as well as read (RD) and write (WR) errors in the 8T SRAM based cache can be detected. As a result, guardbands added for these variations are reduced or eliminated, improving performance and...
Infrequent dynamic events like VCC droops and temperature changes result in the use of a static VCC guard-band. Measured data on a 16KB 8T array featuring tunable replica bits illustrate the opportunity of eliminating a majority of the static guard-band in memory arrays, resulting in lower operating VCC/power.
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