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We demonstrate for the first time the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) with low temperature (LT) processes devoted to 3D sequential integration. The electrical behavior of these TFETs, with junctions obtained by Solid Phase Epitaxy Regrowth (SPER), is analyzed and compared to reference samples (regular process at high temperature, HT). The threshold voltage...
In this paper, for the first time, the reliability of HfO2-based RRAM devices integrated in an advanced 28nm CMOS 16kbit demonstrator is presented. The effect of the introduction of a thin Al2O3 layer in TiN/Ti/HfO2/Al2O3/TiN is explored to improve the memory performances. Thanks to the in-depth electrical characterization of both HfO2 and HfO2/Al2O3 stacks at device level and in the 16×1kbit demonstrator...
Tunneling-based transistors (TFETs) have attracted interest due to their (theoretical) capability of switching more sharply than MOSFETs. However, other mechanisms that take place in SOI devices can provide even more abrupt switching and higher current. We examine the family of emerging TFET-competing devices based on barrier modulation, bipolar amplification and impact ionization. Practical results...
A new floating-body effect in advanced fully-depleted SOI MOSFETs is revealed. Gate tunneling current is responsible for the body charging and may lead to the onset of an abnormal peak in transconductance. This effect occurs even at low drain voltage, is gate area-dependent, and can be modulated by driving the back-gate from weak to strong accumulation. A qualitative analytical model is proposed to...
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