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For the first time the thermal stability of a new fluorine-free (F-free) W barrier coupled with W interconnections enabling 22% line 1 resistance improvement is evaluated in view of 3D VLSI integration. Integrated with ULK, no resistance nor lateral capacitance degradation is observed up to 550°C 5h while preserving good reliability. For additional thermal stability a TEOS/W stability is demonstrated...
In this paper, for the first time, the reliability of HfO2-based RRAM devices integrated in an advanced 28nm CMOS 16kbit demonstrator is presented. The effect of the introduction of a thin Al2O3 layer in TiN/Ti/HfO2/Al2O3/TiN is explored to improve the memory performances. Thanks to the in-depth electrical characterization of both HfO2 and HfO2/Al2O3 stacks at device level and in the 16×1kbit demonstrator...
This work gives insights on the performance levers to optimize nFET Fully Depleted Silicon On Insulator sheet resistance with low temperature activation. Optimum dopant concentration, i.e clusterization limit for arsenic and phosphorus activated at 600°C has been extracted. This study shows that phosphorus appears to be the best candidate for nFET low temperature doping. Solid Phase Epitaxial Regrowth...
In this paper, we address the problem of junction formation with a low temperature processing (≤ 600°C) through Solid Phase Epitaxial Regrowth. We present the main experimental achievements and suggest solutions to optimize the junctions. In particular, atomistic simulations based on kinetic Monte Carlo (kMC) method allow getting insight into the complex physical phenomena that take place during junction...
In this paper, we compare the electrical properties of Ultra Thin Buried Oxide (UTBOX) Fully Depleted Silicon On Insulator (FD-SOI) MOS devices for rotated and not rotated substrate with different gate lengths. We found a significant performance enhancement on FD-SOI PMOSFETs as expected, while keeping a good control of short channel effects. Surprisingly, to a lower extent, an improvement is also...
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