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For the first time the thermal stability of a new fluorine-free (F-free) W barrier coupled with W interconnections enabling 22% line 1 resistance improvement is evaluated in view of 3D VLSI integration. Integrated with ULK, no resistance nor lateral capacitance degradation is observed up to 550°C 5h while preserving good reliability. For additional thermal stability a TEOS/W stability is demonstrated...
While the 3D sequential process is still under development, the electrical influence of specific process for the bottom tier needs to be studied. As another MOS transistor layer is fabricated on top of the bottom one, contamination risk and thermal stability issues appear, thus requiring adaptation of conductors/dielectrics for intermediate Back-End Of Line (iBEOL) processing. As materials differ...
For the first time, Multi-VT UTBOX-FDSOI technology for low power applications is demonstrated. We highlight the effectiveness of back biasing for short devices in order to achieve ION current improvement by 45% for LVT options at an IOFF current of 23nA/μm and a leakage reduction by 2 decades for the HVT one. In addition, fully functional 0.299um2 bitcells with 290mV SNM at 1.1V and Vb=0V operation...
We demonstrate that planar Fully Depleted Silicon-On-Insulator (FDSOI) architectures allow improving the electrostatic control (and in turn the dynamic performance by 22%) and the variability of Complementary Metal-Oxide-Semiconductors (CMOS) devices, compared to the bulk technology. It is thus an ideal solution for Low Power (LP) applications and SRAM stability at the 22 nm node and below. Moreover,...
In this paper we explore for the first time the impact of an Ultra-Thin BOX (UTBOX) with and without Ground Plane (GP) on a 32 nm Fully-Depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50 mV DIBL reduction by using 10 nm BOX thickness for NMOS and PMOS devices at 33 nm gate length. Moreover, the combination of DIBL reduction and...
Sources responsible for local and inter-die threshold voltage (Vt) variability in undoped ultra-thin FDSOI MOSFETs with a high-k/metal gate stack are experimentally discriminated for the first time. Charges in the gate dielectric and/or TiN gate workfunction fluctuations are determined as major contributors to the local Vt variability and it is found that SOI thickness (TSi) variations have a negligible...
In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX thicknesses with or without ground plane (GP). With a simple High-k/Metal gate structure, the 32 nm devices exhibits Ion/Ioff performances well situated for low power (LP) applications. The different BOX thicknesses and ground plane conditions are compared with bulk shrunk technology in terms of variability and noise. 0...
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