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Through Silicon Vias (TSVs) are crucial elements for the reliable operation and the yield of three dimensional integrated circuits (3D ICs). Resistive open defects are a serious concern in TSV structures. In this paper, a post-bond, parallel testing technique is proposed for the detection and location of resistive open defects in TSVs, which is based on easily synthesizable all digital testing circuitry...
Transistor aging, due to Bias-Temperature Instability (BTI) is a serious concern in Static Random Access Memories (SRAMs). Under BTI stress an SRAM cell becomes increasingly skewed, which in turn affects its performance characteristics and consequently the memory reliability. In this paper, a variation tolerant technique for the periodic monitoring of the BTI influence on SRAM cells is presented....
Due to their high density, modern DRAMs are very susceptible to the interactions between adjacent cells, which in turn increases the difficulty and complexity of memory testing. In this work, we studied the interaction mechanisms among neighbouring DRAM cells in order to provide an efficient testing solution. According to the open literature, there are two mechanisms responsible for this interaction:...
The test complexity of high density DRAMs increases with technology evolution, due to a larger impact of process variation and weak defects. In particular, resistive open defects turn to be a major concern in DRAMs. Our analysis and simulation results show that an important phenomenon exists, charge accumulation, which is currently not considered in DRAM testing. Charge accumulation occurs in DRAM...
Timing errors are a major threat in nanometer technology integrated circuits. Razor is a well known timing error tolerance design technique. However, its silicon area cost makes it unattractive for widespread use. In this work, we reuse the Razor topology in order to achieve low power scan testing operations and make this technique a viable solution which will serve both on-line and off-line testing...
Single event upsets (SEUs) that affect adjacent nodes in a design, by charge sharing mechanisms among these nodes, are a great concern in nanometer SRAMs, since pairs of cells are influenced. The concern is also extended to SEU related soft error tolerant latch designs, where multiple memory elements are exploited. In this work, we deal with double node charge sharing SEUs (DNCS-SEUs) that affect...
Timing errors are a major threat in modern integrated circuits. Suitable error tolerance design techniques exist, like Razor, aiming to confront with this situation. However, the silicon area cost of these solutions makes them unattractive for widespread use. In this paper, aiming to broaden the applicability of timing error tolerance techniques, we explore the ability to extend their use for low...
Power-gating structures for intermediate power-off modes offer significant power saving benefits as they reduce the leakage power during short periods of inactivity. However, reliable operation of such devices must be ensured by using adequate test methods. We propose a signature analysis technique to efficiently test power-gating structures that provide intermediate power-off modes. In particular,...
A Build-In Self-Test (BiST) circuit suitable for embedded RF Mixers in System-on-Chip applications is presented in this paper. This is a defect-oriented test scheme that dynamically sets the Mixer to operate in homodyne mode. The DC level generated at its output is used to control the oscillation frequency of a simple voltage controlled oscillator. Deviations of the oscillation frequency from the...
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