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A 65-nm CMOS IC containing a synthesizer, a continuous-time bandpass delta-sigma ADC and associated digital filter digitizes 200–400 MHz inputs with bandwidths up to 100 MHz. With the ADC clock supplied by the internal synthesizer, the observed phase noise on a 430-MHz carrier is −137 dBc/Hz at 750-kHz offset. The gain of the IC is adjustable over a 39-dB range using an LNA in parallel with a resistive...