The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Memory performance has become the major bottleneck to improve the overall performance of the computer system. DDR3 SDRAM is a new generation of memory technology standard introduced by JEDEC, support multibank in parallel and open-page technology. On the basis of in-depth study of DDR3 timing specification, design a DDR3-based memory controller. Memory access control module is the most key component...
When there are several concurrently executing applications in Chip-Multiprocessor (CMP), it's a problem to allocate cache resource between these applications. Cache partitioning is commonly used to solve this problem. Most of the existing partitioning schemes is to reduce the miss rate of concurrently executing applications, but the optimal miss rate does not mean the best performance. This paper...
VCO is the key component in PLLs, and is easy to be interfered by the noise on control voltage or power supply. In this article, a build-in LC filter is inserted into a single-end VCO which is named BF-VCO. The LC filter consists of a regulated cascode active inductor and a capacitor. And the low-pass bandwidth is not greater than 1.6MHz. The measurement spectrum shows that the noise received by the...
When there are several application running on Chip-Multiprocessors (CMPs), it is a problem to allocate the on-chip cache capacities between these competing applications. Cache partitioning is commonly used to solve this problem. Existing cache partitioning schemes either dedicate to the shared design or partition the last level cache depending on limited memory information. This paper presents Private...
Two concurrent transactions are said to conflict based on linearizability semantics if they access the same shared data and at least one of them modifies that data. In many applications enforcing the strict linearizability semantics over the entire read-set of a transaction can lead to a large number of unnecessary aborts. Concurrent threads executing transactions with high contentions can result...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.