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We have successfully developed an alternative SRAM cell using a bulk thyristor-RAM (BT-RAM), which has a 35-nm gate-length with triple selective epitaxy layers (TELs) for the anode, the n-base, and the cathode. The TEL BT-RAM reads and writes at an ultra low voltage of 0.45 V at 900 ps and reads and writes at a high speed of 100 ps at 0.9 V. It also has excellent scalability, a high Ion/Ioff ratio,...
We have successfully developed an alternative SRAM cell for the first time using a bulk thyristor-RAM (BT-RAM) with triple selective epitaxy layers (TEL) for anode, n-base, and cathode. The n-base of the pnp transistor is a key for the thyristor characteristics. We optimized both the thickness and the dopant concentration of the n-base by using an in-situ doped selective epitaxy technique. We obtained...
We fabricated alternative SRAM cells based on a thyristor using SOI and bulk Si wafers, and then compared their performance. A selective epitaxy technique was applied to form anode regions (SEA) for both types. These devices performed extremely well, with high-speed read/write, high lon/Ioff current ratio (>108), and low stand-by current (< 0.5 nA/cell). Write "1" (turn-on) and read...
We developed novel SRAM cells using bulk thyristor-RAM (BT-RAM). BT-RAM, formed on bulk Si wafers, is low cost and has good compatibility with logic process flows. BT-RAM has excellent performance, with a 100-ps read/write, high Ion/Ioff current ratio (> 108), and low standby current (< 0.5 nA/cell). We can expect the ideal cell size to be as low as 30 F2, one-fourth that of a conventional 6T-SRAM...
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