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The single event effects hardening and heavy-ion testing of a radiation-hardened Flash-based field programmable gate array, RTG4, are presented. The hardened logic circuits include fabric flip-flops, fabric SRAM, global clocks, PLL, and SERDES. SEL is hardened for the whole chip. Lastly, the inspace programming is hardened as the consequence of the above hardening activities. Test results show the...
Heavy-ion beam is used to perform Single Event Effects testing on the Flash-based and radiation hardened FPGA, the RT4G150 device. Soft errors due to SEU and SET in the fabric Flip-Flops and PLL generated clocks are measured and analyzed. SEFIs in PLL and SERDES are also observed.
The extension of Moore's Law at the 45/32nm nodes is made possible by the introduction of high-k metal gate. In the gate-last scheme to integrate high-k metal gate, planarization and surface topography control have been reported as some of the biggest process challenges. This paper presents a three-platen chemical mechanical planarization process in which fixed abrasive is used on platen 2 and a non-selective...
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