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This work presents an accurate and efficient closed form model to compute the slew metric of on-chip RC interconnects of high speed CMOS VLSI circuits. Our slew metric computation is based on the Burr’s distribution function. The Burr’s distribution is used to characterize the normalized homogeneous portion of the step response. The simulation results performed on the practical industrial nets justifies...
In case of very high frequency as in Giga-scale (GHz), no longer can interconnects be treated as mere delays or lumped RC networks. The most common simulation model for interconnects is the distributed RC and RLC model. The impact of interconnects on circuit performance in both the analog and digital domains is ever increasing. Unfortunately, this model has many limitations which can lead to inaccurate...
With the increasing levels of on-chip integration, more functional units are integrated onto a single die, the logic delays decrease due to faster transistors. At the same time, local interconnect delays similarly improve because the physical size of circuit blocks decrease, and the local interconnect spans shorter distances. During the interconnect design process, multiple design criteria are considered,...
Due to high packaging density of components, power is increasingly becoming the bottleneck for the design of high performance VLSI circuits. It is essential to analyze how the various components of power are likely to scale in the future, thereby identifying the key problematic areas. This is an important fact because the conventional design, analysis, and synthesis of VLSI circuits are based on the...
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