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We propose a hierarchical approach for the macro level cause-effect physical defect diagnosis in digital circuits. As macros we may consider arbitrary subcircuits or library components (e.g. complex gates) of digital circuits. The faulty macro location procedure is considered as a two step task. First, to locate a subset of suspected faulty macros in a network by using stuck-at-fault (SAF) dictionaries...
In this paper, a new very fast fault simulation method to handle the X-fault model is proposed. The method is based on a two-phase procedure. In the first phase, a parallel exact critical path fault tracing is used to determine all the detected stuck-at faults in the circuit, and in the second phase a postprocess is launched which will determine the detectability of X-faults.
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