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In this paper, a new, accurate method for timing characterisation of synchronous CMOS circuits, described at transistor level, is presented. It is implemented in a computer program SLOCOP. SLOCOP first performs a knowledge based partitioning of the circuit into registers and combinational subcircuits, verifies high level timing rules (clock phasing) and finally detects longest signal propagation paths,...
A robust HiFi digital FM demodulation algorithm is discussed. Simulations demonstrate a performance surpassing analogue top-class receivers: a signal/noise ratio better than 90 dB for a sufficiently large carrier/noise ratio and a distortion level below 0.1% at 1 kHz modulation. For compact VLSI implementation, efficient shift-and-add-based CORDIC and IIR filter algorithms are used.
In this contribution the future of CAD tools for custom design of system VLSI chips will be discussed. In 7 propositions and 7 problem statements it will be shown that a complete separation of system and silicon design is necessary, whereby silicon reusability is of prime concern in a continuously evolving technology environment. Knowledge based synthesis techniques implemented on expert systems will...
A top-down methodology for custom integration of Wave Digital filters is discussed. The design is supported by a CAD toolbox, which starts from filter specifications, uses a bit serial architecture and results in dense layout. This is demonstrated by a 3rd order elliptical filter chip, which works at a sampling rate of 312 Khz. The area is 1.8mm2 in 6??m NMOS technology. As a result of scaling, pole-zero...
A designer oriented CAD-tool for MOSVLSI implementation of digital filters is presented, incorporating new techniques dealing with specific problems of digital-filter design such as finite word lengths, limit cycles and noise.
A new dynamic CMOS circuit technique uses n and p logic trees. An n input gate uses only n+2 transistors. It operates racefree from two clocks ?? and ?? regardless of their overlap time. In contrast to the Domino technique, logic inversion is provided. It can be pipelined with the above (??,??) clocks and has the same functional density as clocked n-MOS for much less power.
A Volterra series based distortion analysis of nonlinearities of op amps and parasitic capacitances ... has been developmed and implemented in the DIANA-SC program. Examples and tests demonstrate the use and the efficiency.
A building block for digital filters requires 0.7 mm2 or 3 mm2 per pole-zero for dedicated respectively programmable realisation, in 6??m technology, with 16 bits words and bitrates up to 10Mbit/sec, which makes it competitive to switched capacitor realisation.
The use of the simulation program DIANA as a completely general design system for switched capacitor networks is presented, Using the example of a fifth order elliptical lowpass filter as a guide, time and direct frequency domain analysis, including all possible effects a.o. aliasing, resistive effects, opamp poles, etc..., as well as sensitivity and noise analysis are demonstrated. The program is...
A CAD system is presented which includes both simulation and layout programs sharing a common data base and supporting different hierarchical design styles of MOSVLSI circuits. The front end is a cell design system with graphical stick-diagram input which is compacted into real layout based on a set of lay-out rules. Circuit and logic description is extracted for mixed mode simulation. Cells are symbolically...
A transconductance amplifier is presented, in which the concept of a variable bias current has been introduced. The bias current is a function of the input signal. This amplifier has a very low standby power dissipation and a high driving capability.
Large on-chip capacitors and inductors have been realized by means of sample and hold functions. They are based on the backward-Euler integration rule of their current-voltage relation.
A new monolithic PCM-encoder is presented. It essentially consists of a single eleven bit double polysilicon capacitor array and an improved multiple access comparator. No unity gain amplifier is required. The circuit meets the CCIT specifications.
The concept of threshold functions and Boolean elements is introduced. It allows for digital macromodeling and mixing logic simulation with transient analysis at device or macromodel level. A simulator for 4-phase MOSLSI even as a transient logic simulator which can be combined with active and passive circuit elementsare presented. The simulation of a 6 bit A/D converter is shown as an example.
A new single stage MOS-Bipolar differential amplifier has 60 dB open loop gain, over 10 MHz unity gain bandwidth, input capacitance below 0.1 pF and less than 200 nV/ ??HZ noise.
The gain?bandwidth product fT of a bipolar transistor is calculated, taking the heavy doping effect in the emitter into account. This effect reduces fT, owing to a larger charge storage in the emitter neutral region and a decrease of the built-in voltage of the emitter-base depletion capacitance.
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