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Scaled CMOS proves to be suitable for the design of transceiver ICs at micro- and millimeter-waves. The effort is presently toward compact and low-power solutions in view of integrating several transceivers on the same chip enabling phased array systems. In this paper we present a 24 GHz receiver, based on a subharmonic direct conversion architecture, designed in a 65 nm node. The local oscillator...
A CMOS frequency multiplier is based on a Pierce oscillator injection-locked by a push-push pair. Compared to traditional stand-alone push-push multipliers driving a selective load, this solution provides a differential output and a larger voltage swing. When driven by a half-frequency VCO, prototypes in 65 nm CMOS demonstrate a 13.1% tuning range at 115 GHz with a phase noise of -107 dBc/Hz @ 10...
This work presents a robust, low area, spectral pure 65 nm VCO for mm-wave applications. The varactor, an inversion mode MOS, takes advantage of the minimum feature provided by the technology to optimize capacitance tuning range and Q. The inductor is a 1 turn spiral. A combination of digital and analog tuning is chosen to lower VCO gain. Prototypes show the following measured results: 11.5% frequency...
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