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The block diagrams of the digital image processing and transmission subsystem are presented. CMOS-sensor for image capture is used. The matroid correcting codes and coded modulation are applied. Simulink-model of the imager is elaborated, which allows determining the coding gain, equal to 5.4 dB, for admissible error probability, equal to 10-6. This coding gain allows decreasing the power consumption...
Architecture and VHDL-entities of the sequential coder and the decoder (codec) of the extended Read-Solomon code are presented. Decoder implements the modified Euclidean algorithm of polynomials division. In the present paper the special attention is given to control algorithm of the key-equation solution blocks. Results of codec designing for rate of 3/4 and correcting ability of 32 are presented.
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