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A simulation approach is presented that allows handling ESD simulation and analysis on a chip-level complexity. In a Monte-Carlo like permutational simulation approach, worst case ESD paths are identified. The simulator is embedded in an ESD analysis framework spanning from the chip protection description to an automated virtual HBM test routine with a respective fail reporting interface. The tools...
A simulation approach is presented that allows to handle ESD simulation and analysis on a chip level complexity. In a Monte-Carlo like permutational simulation approach worst case ESD paths are identified. The simulator is embedded in an ESD analysis framework spanning from the chip protection description to an automated virtual HBM test routine with a respective fail reporting interface. The tools...
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