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A per-core clock generator for the eight-core POWER7™ processor is implemented with a digital PLL. This frequency generator is capable of smooth, controlled frequency slewing, minimizing the impact of di/dt. Frequency can be dynamically adjusted while the clock is running, and without skipping any cycles, thus enabling aggressive power management techniques.
This paper describes an integer-N BB-PFD DPLL architecture for wireline communication applications. The feasibility of the structure is demonstrated by implementations targeting applications in the 8-to-11 Gb/s and 17-to-20 Gb/s ranges. A key challenge associated with this approach is how to achieve the proportional-path latency and gain required for overall low-noise DPLL performance. In particular,...
An all static CMOS (45 nm SOI) all-digital fractional-N PLL has a wide tuning range (from 0.84 GHz to 13.3 GHz, at 1.0 V, 65degC) and supports a broad range of multiplication factors (up to 1,000x) and reference clock speeds (from 2 MHz to 1 GHz). At 125degC the period jitter of the 4.12 GHz clock (206 MHz reference) is 1.1 ps rms (11.4 ps pp) at 1.3 V (52.4 mW), and 2.2 ps rms, (22.7 ps pp) at 0...
In this paper, we extend the partition theory developed by Hartmanis and learns for synchronous sequential circuits to asynchronous sequential circuits. method which utilizes the concept of partition pairs to obtain single transition time asynchronous state assignments with reduced dependence is presented. procedures are also presented for obtaining parallel and serial decompositions of synchronous...
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