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Newly developed dual-rate OLT and ONU SoCs combined with our latest transceivers demonstrate high efficient 10G/1G ONU simultaneous discovery processing and hardware-accelerated dynamic bandwidth allocation of the transmission time according to the requirements.
In this paper, a burst-mode CDR circuit is presented that achieves output-data- jitter reduction of 3dB at jitter frequency of 1 GHz, synchronization to the input data within 14 bits of the burst input, and tolerance to pulse-width distortion (PWD) of +0.22/-0.32UI at 10.3125 Gb/s operation. These characteristics are provided by a CDR architecture with jitter-reduction and PWD-compensation circuits.
The CDR circuit is fabricated in 0.25 mum SiGe BiCMOS technology. The low-speed digital blocks, such as the frequency detector, the up/down counter, the modulator, and the dither generator, are developed using CMOS transistors. The LPF used in the DAC is integrated in the chip. Two power supplies, 3.3 V for bipolar transistors and 1.8 V for CMOS, are used. PONs such as 10G-EPON systems require a burst-mode...
A burst-mode clock and data recovery circuit (CDR) for 10 G-EPON systems is described. We propose a new architecture with a single gated voltage-controlled oscillator (GVCO), a digital frequency detector, and a ΔΣ digital-to-analog converter (DAC). The single GVCO and detector reduce frequency error to less than 2 MHz. The ΔΣ DAC eliminates external devices. Moreover, the simulation results show the...
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