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In this paper, we have introduced a new technique based on simultaneous analysis of output voltage gain vs. frequency and phase vs. frequency for fault testing of analog integrated circuits. An automated test frequency generation method is demonstrated here to select minimum number of test frequencies as stimuli. The introduced technique is applied to three benchmark circuits and the obtained results...
The Paper presents the outlines of the field programmable gate array (FPGA) implementation of real time speech enhancement by spectral subtraction of acoustic noise using dynamic moving average method. It describes an stand alone algorithm for speech enhancement and presents a architecture for the implementation. The traditional spectral subtraction method can only suppress stationary acoustic noise...
This paper demonstrates a 23.5 GHz double stage low noise amplifier using an innovative inter-stage matching technique. The same matching technique is also used at the output of the amplifier for the purpose of output matching. The circuit is designed in IBM .13 mum CMOS process and is simulated using cadence spectre. The simulated responses exhibit a forward gain of 20 dB at 23.5 GHz with a bandwidth...
In this paper, a 36.1 GHz single stage LNA using a simple passive output matching technique is demonstrated. The circuit is simulated in Cadence Spectra with 0.13 mum CMOS process parameters. The simulated results exhibit a forward gain of 11.4 dB at 36.1 GHz and 4.9 GHz bandwidth. Reverse isolation is less than -24.6 dB and the input-output matchings are -30.4 dB and -27.65 dB respectively. The circuit...
This paper presents the design of a 21 GHz UWB differential low noise amplifier. The circuit is designed in IBM .13 μm CMOS process and is simulated in Cadence Spectre. The forward gain of the circuit is 9.72 dB at 21 GHz with a bandwidth of 4 GHz (from 19 GHz to 23 GHz). Reverse isolation is less than -26.4 dB and the input-output matching parameters are -26 dB and -19.5 dB respectively. Noise figure...
This paper demonstrates that inserting a small resistance at the drain of a cascode LNA can be the simplest way of achieving higher bandwidth with only a slight degradation in noise figure. A 36.1 GHz single stage low noise amplifier is designed in 0.13 mum CMOS Process with a simple passive output matching circuit. The circuit is simulated using Cadence Spectre and simulation results show a forward...
This paper presents an improved method of highly accurate supply detection by using a bandgap circuit and its implementation in a comparatively inexpensive BiCMOS process. The process is the vanilla N-well complementary metal oxide semiconductor process technology with added deep N-well and P-well layers. The circuit consisting of a simple bandgap core with a resistance divider produces a supply detection...
In this study we have investigated the effects of variation of silicon substrate thickness on the gain of integrated antennas in on-chip wireless interconnect system. The antennas were fabricated on silicon wafer and the excitation was applied horizontally. Simulation of the test structure has been carried out using ANSOFT High Frequency Structure Simulation (HFSS) program employing the three dimensional...
This work is an investigation to the changes in antenna transmission co-efficient with the change in resistivity of the Si substrate and inter-antenna distance. The antennas were fabricated on Si wafer and the excitation was applied horizontally. The simulation data was obtained from the forward transmission gain using the HFSS program of ANSOFT and an analytical model has been developed using Friis...
In this paper an 18.2 GHz differential low noise amplifier (LNA) is proposed for use in on chip ultra wide band transceiver. We used TSMC 0.35 mum process MOSFET model parameters and the simulations are carried out using Cadence Spectre simulator. The single stage differential LNA shows 22.06 dB voltage gain at 18.2 GHz with a operating frequency band of 7.87 GHz. It achieves 0.4162 dB noise figure,...
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