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The dual-material double-gate (DMDG) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) is the leading contender for sub-100-nm devices because it utilizes the benefits of both double-gate and dual-material-gate structures. One major issue of concern in the DMDG-MOSFET is the alignment between the top and the bottom gate that critically influences the device performance...
A two-dimensional analytical model is presented to study the impact of LACGAS device on the device characteristics. It is demonstrated that LACGAS leads to suppression of short channel effects such as threshold voltage (Vth) roll-off, drain induced barrier lowering (DIBL) and hot carrier effects. It also improves the transport efficiency owing to a greater gate control which is achieved by incorporating...
In this work, the proposed GME-TRC MOSFET structure has been investigated for different negative junction depths (NJD) and different gate metal workfunction difference and its performance improvement over the TRC MOSFET is studied using ATLAS-3D and DEVEDIT-3D. The result clearly depicts that GME-TRC MOSFET exhibits superior performance as compared to TRC MOSFET in terms of threshold voltage roll-off,...
In this paper, we propose a new MOSFET design: Multi Layered Dielectric Four Gate MOSFET (G4-MLD MOSFET) and investigate its device performance through a two dimensional (2-D) analytical model by solving Poissonpsilas equation using parabolic potential profile approach. The 2-D analytical model gives physical insight into the electrical characteristics of this design in terms of surface potential...
In recent years, double gate high electron mobility transistor (DGHEMT) have been introduced to provide better immunity to short channel effects which are inescapable with downscaling of the single gate devices due to fundamental limit on gate-to-channel thickness. Furthermore, in sub 100 nm regime, for lower device aspect ratio, channel thickness also becomes an important parameter affecting the...
In this paper, we propose a novel MOSFET design: Gate Material Engineered-Trapezoidal Recessed Channel (GME-TRC) MOSFET and investigate the effect of the negative junction depth (NJD) for different source drain(S/D) extension on the electrical behaviour of proposed structure. The results are compared with conventional Trapezoidal Recessed Channel (TRC) MOSFET using device simulators-DEVEDIT 3-D and...
A two-dimensional (2-D) analytical solution of electrostatic potential is derived for lightly doped Double Gate (DG) MOSFET in the sub-threshold region by solving Poissonpsilas equation using the parabolic profile approach. The analytical model evaluates surface potential, threshold voltage, sub-threshold slope and sub-threshold drain current. Further, to improve the gate control and reduce the gate...
In the present work, a two-dimensional analytical model for novel device architecture, asymmetric gate stack surrounding gate transistor (ASYMGAS SGT) is presented and its effectiveness in suppressing short channel effects and hot carrier effects is investigated. The model is developed by solving the Poisson equation in cylindrical coordinates assuming a parabolic potential profile in the radial direction...
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