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Method of drain bias sweeping is reported to reduce the gate-induced drain leakage (GIDL) current but with other electrical parameters unaffected for p-type polycrystalline silicon thin-film transistors. It is proposed to be due to local electron trapping in the gate oxide near the drain after drain-bias sweeping such that the gate bias effect is screened. The effects of drain bias sweeping can be...
Different degradation behaviors of n-type poly-Si thin film transistors under dynamic voltage stresses have been demonstrated. Combined self-heating (SH) and hot-carrier (HC) degradation is first observed under a certain dynamic stress, where the device degradation is dependent on the pulse rising time (tr) but independent of the falling time (tf). Absence of the degradation during tf is attributed...
Anomalous "sweeping stress" induced degradation is first observed in n-type metal-induced laterally crystallized low temperature thin film transistors (TFTs). Key stress parameters include the maximum drain bias, the sweeping time and the number of sweeping. Degradation occurs only when the maximum drain bias exceeds a critical value. Both transfer and output characteristic degradation is...
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