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Method of drain bias sweeping is reported to reduce the gate-induced drain leakage (GIDL) current but with other electrical parameters unaffected for p-type polycrystalline silicon thin-film transistors. It is proposed to be due to local electron trapping in the gate oxide near the drain after drain-bias sweeping such that the gate bias effect is screened. The effects of drain bias sweeping can be...
Field enhanced leakage current characteristics of metal induced laterally crystallized polycrystalline silicon thin film transistors (poly-Si TFTs) under hot carrier (HC) stress are investigated, in both forward and reverse measurement mode, with varied stress gate/drain voltages and stress times. Degradation behaviors can be understood by the effect of HC stress on drain electrical field and on bulk...
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