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A novel bias scheme is proposed for non-volatile memory cells arranged in a virtual-ground array that utilizes hot-carrier injections for program and erase operations. By taking two adjacent cells on the same wordline as a unit, and letting the commonly shared n+ region being floating during program and erase, punchthrough immunity is greatly improved. Program/erase speed, endurance, and retention...
Bit interference effects in an ultra-thin body, double-gate, trapped-charge-storage type non-volatile memory cell are investigated through two-dimensional device simulations. Though such device is more scalable and has a larger current drive, it is found that the bit states on the two sides of the ldquocommonrdquo body would interact with each other if the body is too thin. The remote charge effect,...
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