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This paper describes a non-binary SAR ADC architecture that is reconfigurable at production testing time to increase the number of chips that meet a given sampling speed specification, i.e. to improve yield. A non-binary SAR ADC can realize higher sampling rates than a comparable conventional binary SAR ADC, by using overlapping SA ranges so that any errors due to incomplete settling of the internal...
In this correspondence, we give an alternative proof of the direct part of the classical-quantum channel coding theorem (the Holevo-Schumacher-Westmoreland (HSW) theorem), using ideas of quantum hypothesis testing. In order to show the existence of good codes, we invoke a limit theorem, relevant to the quantum Stein's lemma, in quantum hypothesis testing as the law of large numbers used in the classical...
Two gate arrays, 10k gates with 4.6k bit SRAM and 9k gates with 9.2k bit SRAM, have been developed using 1.5??m rule CMOS technology and two layer metallization. They have realized 1.4ns gate delay (2 input NAND, F/0=3, l=3mm) and 18ns address access time. High testability by scan path technique, RAM data throughput mode and automatic test data generation, and efficient logic design by neat CAD support...
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