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We demonstrated 40nm gate length "gate overlapped raised extension structure: GORES MOSFET" without halo implantation and prove that the ultra shallow junction (USJ) could coexist with the reducing parasitic resistance in GORES MOSFET. It is the new concept planar transistor with the gate overlapping the in-situ doped epitaxial extension to break through the trade off relation between reducing...
A raised source/drain extension (RSDE) pFET on (110) Si wafer is demonstrated for the first time with in-situ doped selective epitaxy technology. Roll-off has been effectively improved, resulting from the elimination of ion channeling in (110) Si. Due to the hole mobility enhancement and parasitic resistance reduction, ion of 389muA/mum (Vd= -1.0 V) has been achieved at Lmin around 30nm extracted...
We developed a less layout-dependent epitaxially grown SiGe (eSiGe) source/drain (S/D) technique for pFET. We found that the effective stressor region of eSiGe existed only near the channel and that the volume effect of eSiGe was small. On the basis of this mechanism, a new recess RIE and a new epitaxial growth technology were developed, so that the gate-pitch dependence, S/D length dependence and...
For the first time, a novel CMOSFET structure in substrate strained-Si of lang100rang-channel on rotated wafers is presented. Low Ge concentration (10%) of SiGe layer is used in order to suppress the Vth shift and the mobility reduction caused by high channel doping. We applied Si selective epitaxial growth on recessed S/D region in SiGe layer, which is effective to induce high tensile stress and...
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