The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
As the operating frequency of LSI becomes higher and the power supply voltage becomes lower, the on-chip power supply variation has become a dominant factor which influences the signal delay of the circuits. The static timing analysis (STA) considering on-chip power supply variations (IR-drop) is therefore one of the most crucial issues in the LSI designs nowadays. We propose an efficient STA method...
The use of virtualization technology has been increasing in the IT industry to consolidate servers and reduce power consumption significantly. As a virtualization platform, a large-scale blade server is suitable because it can hold a dozen blades in a chassis with well managed configuration, enabling easy provisioning. To realize an energy-efficient blade server, the network component must deliver...
This paper proposes a CDFG (control data flow graph) generating method from a C program for LSI design. At first, an application program described in C language is analyzed. And a hierarchical CDFG that maintains the program structure for optimal HW assignment is generated. After a generation of the CDFG, every operation in the CDFG is partitioned to data operation or address operation for design...
For deep-sub micron technology based LSIs, conventional stuck-at fault model is no longer sufficient for fault test and diagnosis. This paper presents a method of fault diagnosis for transistor shorts in combinational and full-scan circuits under logic test environment. Description of a short requires a very large number of physical parameters, and hence it is difficult, if not impossible, to describe...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.