The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
As a low cost solution to realize a fine line structure for high density chip interconnection, the thin film organic substrate that adopted the same concept as flip chip RDL (redistribution layers) technology has been developed in this study. The coarse line of a conventional substrate could be refined to a much finer distribution through the application of a thin film process. The thin film layers...
QFN (Quad Flat No-lead) packages become popular in recent years because they provide many advantages over conventional leadframe packages. Due to CTE (Coefficient of Thermal Expansion) mismatch of different materials applied in the package, significant warpage will be generated during QFN packaging process, and may cause yield and reliability issues. In this paper, the warpage of a QFN strip induced...
Pd-coated copper wire bonding is getting more practical applications in electronic packaging because of advantages, such as ease of use, better bonding performance and reliability. ENEPIG (Electroless Ni Electroless Pd Immersion Au) is a prevalent surface finish technique that can realize more flexible substrate design, increase wire density and hence achieve device miniaturization. Study had been...
Epoxy Molding Compound (EMC) is the encapsulation material that can provide mechanical support and protection to IC packages. In the meantime, it is also a key contributor to package warpage. Finite element analysis (FEA) has been widely used in packaging development to improve product performance more efficiently. EMC is usually modeled as piecewise linear elastic material in FEA model for simplification...
Through Silicon Via (TSV) forms electrical feedthrough and makes it possible to vertically stack chips with various functions which including logic, memory, analog and MEMS etc. This paper presents a TSV 3D- heterogeneous integration structure of MEMS sensor array with CMOS readout IC (ROIC) and its fabrication technology. Surface micromaching of sensor array are co-designed with TSV fabrication processes...
Silicon interposer with Through Silicon Via (TSV) has been a promising technology for 3D integration. Good thermal property is one of the advantages. Thermal resistance was usually used to estimate thermal property of a package. In order to obtain thermal resistance of silicon interposer, chip junction temperature needs to be measured. However, it is a challenge to acquire junction temperature Tj...
Warpage is a major reliability concern for IC packages. Package structure, material property and assembly process will all impact warpage behavior, which can be characterized by 3D Finite Element Analysis (FEA). Traditionally, the FEA simulation will only analyze warpage of a free standing package with thermo-mechanical stress induced by Coefficient of Thermal Expansion (CTE) mismatch during cooling...
In this paper, performance difference of fine pitch and normal pitch BGA under thermal and mechanical impact conditions has been evaluated by means of thermal shock test as well as board-level drop test. Influence of solder ball material and PCB pad finish was also investigated. The results reveal that decrease of solder ball pitch could lead to increase of vulnerability. Fine pitch BGA fails more...
A ball grid array (BGA) package based on Si interposer with through silicon via (TSV) was designed. Thermal behaviors of the designed BGA with Si interposer has been analyzed and compared to a conventional BGA with BT substrate in the approach of finite element modeling (FEM). The Si interposer with TSV was then fabricated and the designed BGA package was demonstrated. The designed BGA package includes...
SIM cards have been more and more widely used and the failure of packaging becomes a remarkable issue. In this paper, effects of die thickness and layout, material properties and packaging process parameters on the stress of dies were analyzed based on finite element simulation. The whole simulation includes two main packaging processes: cooling after die attach and molding process. The warpage of...
TiN diffusion barrier layers were deposited on SiO2/Si substrate by ALD method that employed TiCl4 and NH3 as the source and reactant gases, respectively, at a temperature range between 350°C and 500°C. Properties of films, including deposition rate, resistivity, surface roughness and chemical composition, were investigated, and performance of TiN diffusion barrier layer was also verified. Deposition...
The ASIC involved in this paper is a read-out FET array for GEM imaging detector. In the ASIC, 4 (rows) × 8 (columns) units are implemented in an area of 2.5 mm × 2.5 mm. The ASIC is designed with a minimum readout cycle of 100 ns. As a read-out array for imaging detector, the package should be assembled in array form too, thus limits the package size. This paper would introduce the package design...
A low temperature wafer-to-wafer bonding technology for 3D packaging/integration based on Cu-Sn isothermal solidification (IS) technology is introduced in this paper. The fluxless bonding technique using Cu-Sn multilayer composites to produce higher re-melting temperature bonding layer is presented. The structure of the intermediate multilayers and bonding patterns are designed, and the bonding process...
Passive integration is one of the important issues for system miniaturization in wireless applications on different substrate. Integrated inductors were designed and realized on both silicon and planarized ceramic substrate. Planarized ceramic substrate has the advantages such as lower cost than polished ceramic substrate and has other advantages such as lower dielectric constant, higher bulk resistance...
As miniaturization is the permanent pursuit of microelectronic industry, stencil printing technology for flip chip bumping has been contributing to this trend for almost half a century. Nowadays, it's still one of the lowest cost solutions to massive manufacture of IC packaging industry. To meet the requirement of further miniaturization, this paper investigated the realization of fine pitch (about...
NiMoP is one of the most important barrier layers for Cu interconnection. A pretreatment for initiating electroless plating on Si/SiO2 based on palladium ion grains chemisorption on self-assembled monolayers (SAMs) of amidogen of silane coupling agent has been developed. The process and properties of electroless plating NiP/NiMoP compound thin films on Si/SiO2 substrate have been investigated. When...
Different metallization systems and bonding designs of Ag-Sn bonding were investigated to achieve good bonding. The bonding strength was evaluated by shear force. The microstructure of bonding interface was inspected by scanning electronic microscopy and ED AX. Shear force test was performed for as-bonded dice. The test results indicate differences among different metallization systems. The bonding...
On the basis of MIL STD 883 method 1012 and SEMI standard G30-88 and G32-86. purely electrical approaches were implemented to measure the thermal resistance of CSOP24 package. Firstly the temperature sensitive parameter (TSP) was measured and calibrated in a temperature controlled fluid trough. Then proper test conditions including measurement current (IM) and test power PHmiddot were chosen according...
Cu is the key material for both on-chip and inter-chip interconnections. It is the major interconnect material in packaging level, especially in through wafer electrical interconnection (TWEI). Barrier layer is necessary as Cu is easy to diffuse into Si, SiO2 and other dielectrics. Comparing with traditional Ta and Ti based barrier layers, electroless plating NiMoP film has many advantages, such as...
Polymer flip chip (PFC) utilizes stencil printing process and conductive adhesives to electrically connect the contacts of electronic components for low cost and low temperature packaging solutions. Compared with other bumping technologies, stencil printing process is quite simple and compatible with preexisting printing equipment in a surface mount assembly line so that cost-effectiveness will be...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.