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A digital multiplying delay-locked loop (DMDLL) is presented to reduce the low-frequency phase noise and lower the power. The main divider is also turned off to reduce the power. The digitally-controlled oscillator uses the switched biasing technique to reduce the low-frequency phase noise. This DMDLL is fabricated in 40-nm CMOS technology and its active area is 0.0088 mm2. The output frequency of...
Phase-locked loops (PLLs) are widely used in various applications such as processors, consumer electronics, and wireline communication systems. When digital circuits and a PLL with a ring oscillator are integrated together, the power supply noise may degrade the jitter performance of the PLL. To lower the supply-noise sensitivity of a PLL, several approaches [1-5] have been proposed. A passive decoupling...
A 0.3V 10-bit rail-to-rail successive approximation register (SAR) analog-to-digital converter (ADC) is realized in 0.18-μm CMOS process. While the supply is 0.3V, a double-boosted sampling switch and a supply-boosted time-domain comparator are proposed to decrease the on-resistance of the switches and improve the conversion time, respectively. To lower the power, differential dynamic switches are...
A 5–20Gb/s power scalable adaptive continuous-time linear equalizer (CTLE) using edge counting is fabricated in 40-nm CMOS technology. The power of this CTLE is adjusted according to the bit rates to improve the power efficiency. An edge counting technique with an asynchronous clock is presented to adaptively adjust the gain and power of this CTLE. All the measured bit error rates are less than 10...
A low-input-swing AC-DC voltage multiplier using Schottky diodes is presented. The equivalent model of the voltage multiplier is developed and analyzed. To enhance power conversion efficiency (PCE), a matching network is added. For a multiple-stage voltage multiplier, a limiting circuit is added for over-voltage protection. A single-stage/three-stage voltage multiplier with a limiting circuit is fabricated...
Delay-locked loops (DLLs) are widely adopted for clock generation and synchronization in high performance digital systems. The design of analog DLLs has become a challenge due to the trends associated with CMOS scaling, namely, high leakage current, low supply voltage, etc. Consequently, many designers have shifted their focus to digitally-assisted or all-digitally implemented DLLs, which are easier...
A 6-GHz all-digital fractional- frequency synthesizer using an FIR-embedded noise filtering technique is presented. This noise filtering technique is realized in the digital domain without multiple matched analog components. This fractional- frequency synthesizer is fabricated in a 90-nm CMOS process, and it occupies 0.18 . Its power is 28.8 mW with a supply of 1.2 V. The measured out-of-band...
Two 3.6mW D-band divide-by-3 injection-locked frequency dividers (ILFDs) are realized in a 65nm CMOS process. The power consumption is 3.6mW for a supply of 1.2V. By using a second-harmonic enhancement technique, a divide-by-3 ILFD achieves a locking range of 130.01∼132.4GHz. To the authors' best knowledge, this is the first divide-by-3 CMOS ILFD to work at D band.
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