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We demonstrate the shortest Ge-channel pFETs reported to date (Lg=30 nm), on Ultra Thin GeOI obtained with the Ge enrichment technique. The Ion/Ioff ratio is raised to a record value of more than 5 decades thanks to the combination of a low defectivity, a thin Ge layer, well-controlled VΛ and SCE. This ratio could be even further improved using of germanidation, raised S/D, no channel doping, and...
For ultimate MOSFET scaling, ultra thin body and BOX SOI transistors have become of great interest, as they are known to dramatically reduce short channel effects (SCE) while maintaining very high device performance. In this work, we emphasize the impact of the substrate / BOX interface space charge conditions on the drain induced barrier lowering (DIBL) increase with gate length reduction, as this...
Scalability of both unstrained and strained FDSOI CMOSFETs is explored for the first time down to 2.5 nm film thickness and 18 nm gate length with HfO2/TiN gate stack. Off-state currents in the pA/mum range are achieved for 18 nm short and 3.8nm thin MOSFETs thanks to outstanding electrostatic control: 67 mV/dec subthreshold swing and 75 mV/V DIBL. For such thin bodies, the buried oxide fringing field...
A new experimental technique is used to analyze the transient response of partially depleted SOI devices to pulsed laser irradiation. This new technique allows calibration of the deposited charge in the sensitive volume (i.e., the body region of the measured SOI transistors) and then the quantitative analysis of the device transient response. In particular 50-nm gate length SOI transistors have been...
A new experimental technique is used to analyze the transient response of partially depleted SOI devices to pulsed laser irradiation. This new technique allows calibration of the deposited charge in the sensitive volume (i.e. the body region of the measured SOI transistors) and then the quantitative analysis of the device transient response. In particular 50-nm gate length SOI transistors have been...
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